[Fpga-synth] Starting points?

[Mike Ravkine]

Theo Verelst wrote:
> As someone who'd built my own logic from electronics even already in the
> 70s it always strikes me that contrary to the well-formed TTL family
> logic for instance, all HDL designs I've witnessed the last years, even
> factory supplied ones (Maybe with the exception of tailored RTL) are
> comparison wise almost extremely under-specified in terms of fundamental
> behavior of parts and connections and timing associated with those, and
> margins and such, so that like with spread out delay and setup and hold
> time and drive line characteristics in TTL, a lot still depends on trial
> and error, preferably with for instance on-fpga probes (like Agilent I
> seem to remember has special interfaces and test software for).
>
>   

Note: My background is verification (and a little design), mainly of 
3-10M gate DSP ASIC SoCs...

I will first admit that I've never done anything more complex then a 
4-bit ALU in TTL (in university, I think we were in the last few classes 
to touch it), but it was a nightmare to implement as compared to the 
12-line RTL version of the same block..

I guess I don't understand why you would want to specify analog things?  
Forcing you to think about non-digital things like setup and hold seems 
to me like the main problem (and handicap) with TTL design.

In an FPGA, things will be placed by P&R where-ever there is room and 
the externally-specified timing constraints can be met.  FPGA synthesis 
tools have all types of tricks like logic replication already up their 
sleeves.. It's likely going to do a better job then you could by hand, 
assuming your design is a moderately large one.  The trial and error you 
speak of happens when clock constraints couldn't be met either by 
synthesis or placement, but this is reported in the compile logs before 
you even load the bitstream on the FPGA, and generally it just means 
your paths are just too long and you have to add some pipeline stages. 

In an ASIC, it's even worse .. a designer could in theory come up with a 
floor plan, but he doesn't know what the analog characteristics of the 
cells he's designing with are! The technology library usually hasn't 
been chosen until after the design is done and verified in simulation 
(using a generic un-timed library).  Once a foundry and technology is 
chosen, a 'trial synthesis' and 'trial static timing' will be run using 
the timed library and again any errors have to be resolved before the 
design hits hardware.  Without going into detail as to what scan, BIST 
and ATPG are (these are ASIC-only things, largely concerning production 
testing), lets just say that additional tools are run on the 
post-synthesis hardware and will do some "stuff" to your design that you 
could not possibly predict.

It seems to me either impossible or unfeasable to specify up-front the 
analog characteristics of a modern digital design..  the best you can do 
is follow general design guidelines like flopping the output of every 
multiplier, maximum number of logic stages between pipeline stages, 
etc.. but all of that stuff is very technology dependent, unless you 
always code for the lowest common denominator (and what fun is that..)

--Mike