[Fpga-synth] Starting points?

[Theo Verelst]

On Sat, 2009-03-07 at 01:33 +0100, Magnus Danielson wrote:
> Dave Manley skrev:
> > Magnus Danielson wrote:
> > 
> >> VHDL being an ADA decendent has typing being HARD. This can be a bit 
> >> annoying for a C programmer like yourself, but eventually you pick up 
> >> on it.
> > 
> > Not to start a language war, but before choosing between VHDL and 
> > Verilog, go look at some code in both languages.  As a C programmer, you 
> > may find Verilog more to your liking.
> 
> Well, being a C programmer myself before hitting onto HDL of any sort, I 
> learned VHDL and sticks with it. When I do HDL design work typing it in 
> VHDL isn't a limiting factor at all really. What is important is to keep 
> tidy code and know that you get exactly what you want. Looking at 
> synthesis outputs will eventually be very rewarding as it may trigger 
> alarm clocks.
> 
> I think people are making much more fuzz about the VHDL then motivated.
> But then again, maybe I am biased as I have seen too much poorly formed 
> Verilog code. Familiar syntax can be a curse rather than a cure.
> 
> Cheers,
> Magnus


As someone who'd built my own logic from electronics even already in the
70s it always strikes me that contrary to the well-formed TTL family
logic for instance, all HDL designs I've witnessed the last years, even
factory supplied ones (Maybe with the exception of tailored RTL) are
comparison wise almost extremely under-specified in terms of fundamental
behavior of parts and connections and timing associated with those, and
margins and such, so that like with spread out delay and setup and hold
time and drive line characteristics in TTL, a lot still depends on trial
and error, preferably with for instance on-fpga probes (like Agilent I
seem to remember has special interfaces and test software for).

The nice and preferable 'correct by construction' paradigm like in
Pascal (or C of course, to an extend) seems really not so readily
achievable, if even at all, which is kind of a shame, I would think.

The suggestion of 'soled and unbreakable logic', in general, is
seriously deluding, anyhow, regarding of the HDL language. I even prefer
schematics from the manufacturer because some of the problems are than
more over viewable and like the historic logic design process was fairly
successful, alas lossing portability across brands. Opencores for
instance does not clearly prove to my anyhow that all the activities of
those kinds are a huge succes, or at least they are far from insightful,
and I notice most public shared designs, and I suppose many closed
source ones, too, are made often for a even a specific target chip.

   happy moonlighting (compared to bankrupt Moog and the dead president
society, anyhow,

   Theo Verelst
   http://www.theover.org/