[Fpga-synth] Starting points?

[Mike Ravkine]

Magnus Danielson wrote:
> I think people are making much more fuzz about the VHDL then motivated.
> But then again, maybe I am biased as I have seen too much poorly 
> formed Verilog code. Familiar syntax can be a curse rather than a cure.
I took several VHDL courses in university, and let me tell you, some 
folks will write poorly formed code in ANY language, no matter how 
strongly typed.  You're right though, Verilog certainly lets you get 
away with a lot of things it shouldn't.  A good linting tool is a must.

VHDL is good to start with because it will do it's best to force you to 
think out what you want to make.  Once you've learned to do this with 
coercion however, and can just crank out pure RTL .. VHDL becomes 
unnecessary verbose.  I recently ported/cleaned up one of my old VHDL 
designs to Verilog, and files shrank 20-50% (go go gadget anecdotal 
evidence).

With all that being said, learning both languages can only improve your 
understanding of hardware design :)

--Mike