[Fpga-synth] Starting points?

[Magnus Danielson]

Dave Manley skrev:
> Magnus Danielson wrote:
> 
>> VHDL being an ADA decendent has typing being HARD. This can be a bit 
>> annoying for a C programmer like yourself, but eventually you pick up 
>> on it.
> 
> Not to start a language war, but before choosing between VHDL and 
> Verilog, go look at some code in both languages.  As a C programmer, you 
> may find Verilog more to your liking.

Well, being a C programmer myself before hitting onto HDL of any sort, I 
learned VHDL and sticks with it. When I do HDL design work typing it in 
VHDL isn't a limiting factor at all really. What is important is to keep 
tidy code and know that you get exactly what you want. Looking at 
synthesis outputs will eventually be very rewarding as it may trigger 
alarm clocks.

I think people are making much more fuzz about the VHDL then motivated.
But then again, maybe I am biased as I have seen too much poorly formed 
Verilog code. Familiar syntax can be a curse rather than a cure.

Cheers,
Magnus