[Fpga-synth] Starting points?

[Dave Manley]

Magnus Danielson wrote:

> VHDL 
> being an ADA decendent has typing being HARD. This can be a bit annoying 
> for a C programmer like yourself, but eventually you pick up on it.

Not to start a language war, but before choosing between VHDL and 
Verilog, go look at some code in both languages.  As a C programmer, you 
may find Verilog more to your liking.

A basic tutorial is here:

http://www.asic-world.com/verilog/veritut.html

or in a pdf:

http://www.inf.ed.ac.uk/teaching/courses/cd/VerilogTutorial.pdf

-Dave