[Fpga-synth] Starting points?

[Mike Ravkine]

Magnus Danielson wrote:
> VHDL being an ADA decendent has typing being HARD. This can be a bit 
> annoying for a C programmer like yourself, but eventually you pick up 
> on it.
>
All of this is true, but you can save yourself a lot of un-necessary 
type-coverting pain by skipping past VHDL and just learning Verilog.  
Then again I was personally forced to go through VHDL first, and it 
probably made me a better hardware designer due to it's anal-retentive 
nature :)

In either case, free simulators are avilable for both languages .. the 
best way to learn is to pick something simple .. say, a counter. Design 
it and test it.. then add features (up/down, clear, preset, etc..) and 
test it again..  Then, try building a state machine..  Learn about 
pipelining, and all the other stuff that Magnus talked about.
>
> You will also have to learn to build testbenches. I cannot stress the 
> importance of that to aid towards your sucsess. A good testbench 
> generates a bunch of signals and confirms the responses from the DUT.
SystemVerilog is really effective for building testbenches.. it works 
with both VHDL and Verilog designs, and allows object-oriented classes 
to be instantiated alongside and communicate with your prototype 
hardware, alongside built-in means to automatically gather and report 
the test results.  Unfortunately, I don't think there are any free 
simulators.  However, even just Verilog has the ability to do 
hierarchical references, which makes writing testbenches much easier 
then VHDL.

> You should also learn to number your buses downwards:
> signal data : std_logic_vector(31 downto 0)
> or by using the generic N:
> signal data : std_logic_vector(N-1 downto 0)

It's really funny that you bring this up :)

Today at work, the ASIC design manager and one of our most Senior ASIC 
designers were talking about adding this rule to our 
(manditory-to-pass-cleanly) lint checker.  

The manager wanted to enforce this rule company-wide, but the designer 
pointed out that if you're making a right-shifting single bit delay 
chain (data always seems to go left-to-right on any dataflow diagram 
I've seen), then numbering your bus 'backwards' in the rtl has the 
desirable aspect of the least delayed version being delay[0], the next 
delayed version is delay[1], etc..

I guess you could just shift left instead...

--Mike