[Fpga-synth] SVF Question

[Eric Brombaugh]

Scott Gravenhorst wrote:
> Happy New Year all,
> 
> Is there a web resource which explains why a digital SVF is best operated using low cutoff frequencies?  
> 
> I've read a small piece on Chamberlain who used a figure of 1/6 SR.  Other people suggest 1/8 or even 1/16 SR as an upper Fc limit, but the explanations I've read are sort of vague saying things like "certain features aren't apparent in the digital version as are available in the analog version when the digital version is used at higher cutoffs".

I'd try asking this question on comp.dsp. If you can get a reply from 
Robert Bristow-Johnson you'll have the last word. If that doesn't work, 
I'm sure you know about dsprelated.com - I haven't found the answer 
there myself, but you might be able to dig it out.

To answer the question you didn't ask: My gut feeling is that this is 
fairly normal behavior for a recursive sampled system. In my day job 
designing communications & control systems it's fairly common to specify 
that closed-loop controllers operate with at least a 20:1 ratio of 
sample rate to system bandwidth.

The reason for this is that many linear systems are designed using 
classical techniques - bode plots, S-plane analysis, traditional 
prototypes like bessel, tchebyshev, butterwort, etc and then converted 
from continuous to discrete. The trouble with this is due to the 
frequency warping of the bilinear transform which is often used for the 
conversion. Since it tries to map the entire jw axis onto the z unit 
circle, there is considerable distortion of frequency response as you 
get closer to Fs/2. This results in fairly marked deviation from ideal 
classical behavior in sampled systems based on continuous concepts at 
higher frequencies. Since the Chamberlin SVF is basically an 
approximation of the common continuous SVF, perhaps it's underlying math 
starts to fall apart as you get closer to nyquist.

Eric