[Fpga-synth] New FPGAs

[Magnus Danielson]

Nicholas Gregorich skrev:
> The DDR hard IP is interesting, closing timing on high speed DDR designs 
> is not trivial. Along with the announcement from Altera today (high end 
> Stratix IV GT with 11.3 Gbps transceivers and mid range Arria II GX with 
> 3.75 Gbps transceivers and PCIe hard IP) its obvious that high speed 
> transceivers are currently driving the FPGA market.

Depends on what you do, but it is a heavy dope when you do more high-end 
stuff. Building large busses doesn't work as it use to, you need the 
pins for memory interfaces. The DDR hard IP is a late but welcome addition.

MGTs in the 10 GB/s range is needed for a varity of interfaces.

PCI-X solves another issue, wide control-bus.

Parallel can be used in the neighborhood and serial if you are going 
anywhere... but as speed rises the "neighborhood" shrinks and we want 
pins for other things. Serial links within boards is becomming a 
necessity and besides, isn't big magic anymore.

It is good that the V6 and S6 is released, now we want the silicon also. 
Xilinx has to start running again since they have lost pace and Altera 
got into distance of them. The competition just got healthy.

Cheers,
Magnus