[Fpga-synth] Linear / Expo Release for ADSR Working

[Scott Gravenhorst]

"The making of synthesizers in FPGAs." wrote:
>
>On Mon, 2009-04-06 at 16:51 -0700, Scott Gravenhorst wrote:
>> Have a listen:
>> 
>> http://home1.gte.net/res0658s/gatemanpoly_bell_lin_expo.wav
>> 
>> This is a sample of two strikes of a bell sound, the first uses 
>linear release, the second uses > exponential release. There is a 
>marked difference, especially near the end of the fade out. > > 
>For those interested... 
>
>Hi Scott,
>
>I am going to make the gateman into a software simulation, in C, but
>maybe you have that already ? 

No I haven't done that.  The only thing I do in C is model idea bits before I code
them in Verilog.  To be honest, I started playing with digital synthesis with a PC
and assembly language.  I didn't really get very far with that because the mobo I
used had rather slow I/O.  It became apparent that I'd either have to buy something
better.  At that point in time, Jim Patchell showed me his Spartan-3E Starter Kit
board at a Synth-DIY meet up and I was mesmerized.  I ordered one that week.  Ever
since then, I slogged through learning Verilog and learning how to think more like a
digital designer (which seems to be an ongoing process).  I'm now at a point where I
believe that I can implement pretty much anything I can understand.

For the time being, I've been quite pleased with the progress I've been able to make
with FPGA synthesizer designs.  One thing I really appreciate about using an FPGA is
that there's _nothing_ else going on other than my design.  I never did like the idea
of using a linear execution CPU and dealing with other stuff that goes on because of
an OS, I/O device interrupts, memory management, etc.  Once I got my head around the
idea of parallelism in an FPGA, I really just abandoned any idea of using a Pentium
for a synth.  I'll leave that to other more patient and knowledgable people. 
Besides, I now have a collection of boards: four S-3Esk, two Avnet Spartan-3A, and
one Spartan-3A DSP 1800 board.  With this, I've got plenty of capacity to put
together a pretty serious ensemble of just my own synth designs.

>I would seem fun to me to take the FPGA design and simulate the exact
>datapath in software (probably as a realtime Jack/alsa midi program),
>which would also be very good for assessing accuracy and even sampling
>issues and of course to try out stuff more easily like different ADSRs.
>It is possible I also turn my DSP synthesizers datapath into a Linux
>program, I know that one at least sounds good (too, there are many
>softsynths) and it's source is alread in C, except the Signal Processing
>interrupt loop loop and IO are different.
>
>The blocks could be connectable over my Bwise (http://wiki.tcl.tk/Bwise)
>but I didn't make such type of app with it yet (I have in the past
>though).
>
>Kind regards
>
>   Theo Verelst
>   http://www.theover.org/wiki/index.php/FpgaSynth
>
>P.S. In case your open source license or your own mind have problems
>with this let me know.
>
>
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>

-- ScottG
________________________________________________________________________
-- Scott Gravenhorst
-- FPGA MIDI Synthesizer Information: home1.gte.net/res0658s/FPGA_synth/
-- FatMan: home1.gte.net/res0658s/fatman/
-- NonFatMan: home1.gte.net/res0658s/electronics/
-- When the going gets tough, the tough use the command line.