[Fpga-synth] Clocks and Enables

[Magnus Danielson]

Mike Ravkine wrote:
> I second this strategy, it's exactly how I implemented my synth.
> 
> Xilinx seems to have some information on their async FIFOs available at:
> 
> http://www.xilinx.com/support/documentation/ipmeminterfacestorelement_fifo_asynchfifo.htm 

If you have two unlocked clocks, asynchronous FIFOs is the way to go in 
general. You can usually get by on 3-8 words in the FIFO.

If you have two unlocked clocks, but data rate is sufficiently low for 
any of them, you can implement handshaking over the clock boundary which 
is safe (using two DFFs in series to clock the signal in from the other 
side). This will avoid asynchronous FIFOs for a slightly more complex 
upfront design. You however need to guarantee that the minimum time 
between words to be transferred is longer than the worst case transition 
time for the hand-shaking design. The goal is that the word sampling 
occurs when the data is stable from the other side. The whole issue is 
really that you want to make sure you sample at the correct time to 
avoid meta-stability and that handshaking ensures that no sample is 
dropped or sampled twice. The normal meta-stability handling is only 
performed at the handshaking. This method is simpler in design, but pays 
by less performance.

If you have two locked clocks, you can get by with simpler approaches, 
since the clock ratios is known and the phase relationship is 
(relatively) stable. Control and fifo can be much simpler in this 
particular case as you have a statical pattern to handle.

Cheers,
Magnus