[Fpga-synth] Clocks and Enables

[Alessandro (Alex) Fasan]

You want to insert a FIFO between the FSM (ClkF domain) and the DAC
(ClkDA domain)  (maybe that's what you mean by double-buffering?).

The FIFO will work on one side with the FSM, this actually should be
very fast.. i believe the only case will be Freq of ClkF > Freq of
ClkDA.

The FSM should write to the FIFO until the FIFO is full (or 90% full
as a watermark), maybe writing say 64 samples at the time.
The DAC will keep reading from the FIFO at its own pace, smoothly.

I would add to the FIFO a low-watermark (say 10% full) and produce a
"almost-empty" signal to signal the FSM to hurry up :) (this is the
equivalent to an interrupt in a micro processor system...)

I am not sure if with Xilinx you have to add synchronizers to the FIFO
control logic ,,, a general FIFO macro should already these.

Hope the above helps.
 Alessandro


On Sat, Sep 13, 2008 at 9:12 AM, Scott Gravenhorst <music.maker at gte.net> wrote:
> I think I know what the answer is, but I want to bounce this the list:
>
> All of my past synth projects have used a single clock.  The enable signal from the DAC module was always exactly one clock period long.  Because of that, I was guaranteed one and only one rising clock transition during the DAC enable signal (because the DAC used the system clock directly) and there was no need to guard against the DAC enable forcing the computation state machine to start more than once per enable.
>
> At least one future planned synth project will do things differently:
>
> There will be two clocks: a DAC clock and a computation state machine clock (or system clock).
>
> a: The DAC's main is controlling the width of the DAC enable signal.
> b: The system clock is faster than the DAC clock.
>
> There are then two conditions to consider depending on the ratio of these two clocks.
>
> 1) The system clock is less than twice the rate of the DAC clock.
>
> In this case, there can be only one rising edge of the system clock while the DAC enable signal is asserted.  So I can just sample the DAC enable signal at each system clock to coordinate the starting of the computation state machine.
>
> 2) The system clock is twice or more than twice the rate of the DAC clock.
>
> In this case, there can be one or more rising edge of the system clock while the DAC enable signal is asserted.  To avoid restarting the state machine after it has already started, I can code to sample the DAC enable signal at every system clock, if DAC enable is asserted, the system enters a state that samples DAC enable until it is not asserted.  Once no longer asserted, the code can perform initialization followed by whatever computation.
>
> In both of the above circumstances, I think I am advised to use double buffering for the data that will be sent to the DAC.  The computational state machine will clock it's output into the "NextDACval" register (using system clock).  The DAC enable signal with the DAC clock will transfer the data from the output of NextDACval into DACreg which feeds the DAC module.  Of course, it must be known that the computational state machine finishes at least one full DAC clock ahead of the next DAC enable signal.
>
> Am I on the right track?
>
>
>
>
> -- ScottG
> ______________________________________________________________
> -- Scott Gravenhorst
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