[Fpga-synth] impact failing to pick up changes?

[Mason]

Hey all,
    So I'm using ISE 10.1.02 now, and I'm wondering if anyone else is 
running into this bug:
    I compile a design, flash it to the FPGA in JTAG mode, and it runs. 
Then I make a small change (I've been playing with a basic LED test; the 
change would be something like the size of the register that gets 
counted through) and regenerate everything. I flash the new file to the 
FPGA, and the old bitfile gets transferred.
    I know I asked the list about this same problem back in the 9.1 era, 
and even called Xilinx about it and they said the issue was selecting 
the wrong clock (i.e. not the JTAG clock) when generating the bitstream.
    So I've changed that, thinking maybe that bug was still there, to no 
avail.
    So, my fellow people programming Xilinx boards, how on earth are you 
doing it?

(I'm using the 3AN starter kit, with libusb under linux, if that changes 
anything.)