[Fpga-synth] unpredictable bus endpoint behaviour

[Edward King]

Disregard.

Twas a malformed packet issue :o(

EK


Edward King wrote:
> I am using pci express endpoints (virtex 5) for some bus interfacing
> stuff. However, the retry buffers are behaving rather unpredictably.
> They effectively lock up every dozen or so cycles and nothing but a
> chip reset will free them....
> 
> I know this isnt a common technology in diy-synths, but I was hoping
> that at least one other person had tried this out and if so, if
> anyone is familiar with this problem?
> 
> EK
> 
> 
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