[Fpga-synth] Hardware-emulation problems

[Rainer Buchty]

Hi everyone,

a former student of mine and I are still working on an Ensoniq SQ80 
VSTi; while making this one more realistic, we did some measurements 
which turned out to not quite show the expected behavior on some 
occasions:


(1) Synchronization

The oscillators are just plain 24-bit phase accumulators of which, 
depending on selected wave size and address resolution, a window of at 
least 8 bits is used for waveform addressing.

If you then e.g. synchronize a 50% square wave to another wave running 
at more than twice the speed you would expect DC output, right? So 
that's what we implemented:
 	http://itec.uka.de/~buchty/const_sq8L.gif

However, doing measurements on the real machine showed not DC but just 
some sort of impulse response -- a short spike:
 	http://itec.uka.de/~buchty/const_sq80.gif
 	http://itec.uka.de/~buchty/const_sq80_zoom.gif

Does anyone have an explanation what might be going on here that we see 
that "chirp" instead of the expected DC?


(2) DCA

The DCA on that very soundchip is a multiplying DAC. One input is the 
volume data, the other one the waveform data. Whether volume data DAC
generates the reference voltage for the waveform DAC or vice versa is 
unknown.

When modulating the volume with an LFO you would expect discrete steps 
with the step width referring to the update ratio. Hence, we implemented 
this:
 	http://itec.uka.de/~buchty/pics/dca_sq8L.gif

The idea is that when we drop from max to min (0) volume level, we 
would see a likewise response, i.e. the signal output 
dropping to 0.

Well, in reality it doesn't. Instead, in the original hardware we found 
this behavior:
 	http://itec.uka.de/~buchty/pics/dca_sq80.gif

You basically see an averaging effect, especially noticeable at the 
volume drop from max to min, pausing on max/2 for half an update cycle.

While I studied the operating system sources, I didn't find an immediate 
sign that this is a software function (which I suspected for the nicely 
halved step durations) -- I might have overlooked something there, of 
course.

But in case I didn't: is there any half-way decent explanation for such 
behavior in multiplying DACs?


Rainer