[Fpga-synth] hello_world\LEDs\counter_integerLEDs

[malik martin]

though those questions still stand,
I did manage to modify it. I hope it doesn't look too C styled :P

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

// email: music.maker at gte dot net
`timescale 1ns / 1ps
// counterLEDs.v
// Scott R. Gravenhorst(modified by Malik Martin)
module test(led,sw,CLK_50MHZ);
    output [7:0] led;
  input [1:0] sw; //0 == on/off  1 = clock/clock*0.5
  input CLK_50MHZ;
    reg [29:0] cnt;
  reg [1:0] swdata;
  reg toggle;  //will be used for clock*0.5
  reg ledtest;

  // initialize all register bits to 0.
  initial   begin     cnt = 30'b0;   end

  assign led = cnt[29:22];               // display the high bits of the

    always @(negedge CLK_50MHZ)
  begin
   toggle <= toggle + 1;  //start half clock, but don't use it yet
   swdata <= sw;     // send initial signals

   if(led == 0)     //indicates weather
    ledtest <= 0;    //the LEDs have
   if(led == 8'b1111_1111)  //gone high or low
    ledtest <= 1;    //on all 8 bits

   if(ledtest == 0)  //if == 0, count positive
    if(swdata[1] == 0)  //half clock off
     if(swdata[0] == 0) //if sw[0] is low
      cnt <= 30'b0;  //then the LEDs are off
     else
      cnt <= cnt + 1; //else they're on
    else   //else half clock on
     if(swdata[0] == 0)
      cnt <= 30'b0;
     else
      if(toggle == 1)
       cnt <= cnt + 1;
   if(ledtest == 1)   //same but in reverse
    if(swdata[1] == 0)
     if(swdata[0] == 0)
      cnt <= 30'b0;
     else
      cnt <= cnt - 1;
    else
     if(swdata[0] == 0)
      cnt <= 30'b0;
     else
      if(toggle == 1)
       cnt <= cnt - 1;

  end    // clock triggers an increment of cnt
endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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