[Fpga-synth] hello_world\LEDs\counter_integerLEDs

[malik martin]

Hi guys,
   Have a few questions about this introduction stuff here in the
counter_integerLEDs project.
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

// email: music.maker at gte.net
`timescale 1ns / 1ps
// counterLEDs.v
// Scott R. Gravenhorst
module test(led,CLK_50MHZ);
    output [7:0] led;
  input CLK_50MHZ;
    reg [29:0] cnt;

  // initialize all register bits to 0.
  initial   begin     cnt = 30'b0;   end

  assign led = cnt[29:22];               // display the high bits of the
    always @(negedge CLK_50MHZ)  begin    cnt <= cnt + 1;  end    // clock
triggers an increment of cnt
endmodule

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

reg[29:0] cnt;
why did you choose to make this value 30 bits? Just to make the LED
iteration visible to the human eye?
assign led = cnt[29:22];
again, the same question. this is what it looks like.

always @(negedge CLK_50MHZ)  begin    cnt <= cnt + 1;  end
is there a reason you set it to the end of the inc cound and not the
beginning? does the negedge or the cnt + 1;
do this opposed to posedge 1+cnt; ?
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