[Fpga-synth] Stereo Audio Interface update

[Eric Brombaugh]

The I2S DAC is working with the Avnet EVK board. I've put the initial  
test code up on the website:

http://members.cox.net/ebrombaugh1/synth/audiodac/i2s_tst.zip

This is a Verilog ISE 9.2 project that uses the capsense pads to raise  
& lower the pitch and gate the tone on/off. Make a slide whistle or  
morse key! This test runs the DAC at 24-bits & 41.7kHz, but I'll be  
updating the core logic to run faster in the near future.

Eric