[Fpga-synth] Try out spartan3e projects, questions

[Magnus Danielson]

> I'm currently working on a design with two Virtex-5 330T parts and while 
> it is true the primitives may be rated at 500MHz, those primitives must 
> be connected to each other.  If you have any significant combinational 
> depth and route complexity the max clock speed will rapidly drop to a 
> few hundred MHz even with significant pipelining and floorplanning.  I'm 
> not saying it is impossible, but running a complex design at the rated 
> speed of the device is difficult.  125MHz is easy, 250MHz isn't bad, 
> 300+ starts to get hard.

Agree.

The trick to go upspeed and succseed is not attempting to fill the FPGA. 
We consider 70% as "full". Beyond that will placement become more and 
more lengthy and unpredictable, both in convergance and convergance time.

BRAMs and MULT blocks can be fully utilized most of the time, but LUTs 
is harder, they require headroom.

Fiddeling with synthesis options can be a worthwhile process. You can 
trade between area and speed. Duplicating circuits can make route and 
placement easier and thus allow higher speeds. Avoiding it means less 
area but lower speed. There are many things like that. Taking time to 
make some designs "fit" better is certainly worthwhile. That's where 
much of the engineering time goes. Small resource usage and much 
functionality. It is always rewarding when one finds that combination. 
But you have to start early in trying to make the big picture fit. Also 
trying to get all of the key aspects on the table, or the redesigns will 
take both more time and resources than a propper design. It is also 
important to have a clear view of the nitty gritty aspects so that not 
too much is hacked in later.

Cheers,
Magnus