[Fpga-synth] Try out spartan3e projects, questions

[Dave Manley]

Eric Brombaugh wrote:
> Dave Manley wrote:
>>
>> I'll chime in with one comment: the max FPGA frequency is no where 
>> near the max frequency of modern processors.  I haven't looked at 
>> DSPs in a long time, but assume some must be able to run in the GHz 
>> range, while most FPGAs are going to be limited to a few hundred MHz 
>> at most (with any significant amount of logic).  In terms of clock 
>> speed only, what is the fastest DSP out there?  I see some AD 
>> Blackfin rated at 750MHz.
>
> True, but it depends on what type of FPGA and DSP your talking about. 
> A Spartan 3E probably tops out around 250MHz if you're lucky, but 
> that's a $15 FPGA. I'm using some high-end Virtex5 parts that can run 
> > 500MHz internally and have 640 MAC units. Lets see - that works out 
> 320GOPS max. Name me a DSP that can get anywhere close to that? Of 
> course, that's cheating a bit - that part costs $2500. :)
>
> The big advantage of FPGAs is parallelism - even on a low-end part you 
> can clock all those registers, multipliers and RAMS simultaneously. 
> Even high-end DSPs with multiple execution units (normally no more 
> than 8 or so) have bus bottlenecks that will prevent you from keeping 
> those resources busy all the time.
>
> The big advantage of DSPs is flexibility - it takes only fractions of 
> a second to reconfigure a DSP for a completely different task (ie, 
> load a program), or to compile & debug code. The FPGA configuration 
> process is slower and the compile times can take hours.
>
> There's a lot of overlap though and you can use both technologies to 
> accomplish many of the same things. If your only tool is a hammer...
>
I'm currently working on a design with two Virtex-5 330T parts and while 
it is true the primitives may be rated at 500MHz, those primitives must 
be connected to each other.  If you have any significant combinational 
depth and route complexity the max clock speed will rapidly drop to a 
few hundred MHz even with significant pipelining and floorplanning.  I'm 
not saying it is impossible, but running a complex design at the rated 
speed of the device is difficult.  125MHz is easy, 250MHz isn't bad, 
300+ starts to get hard.

-Dave