[Fpga-synth] Stereo Audio Interface

[Magnus Danielson]

> Nicholas Gregorich wrote:
>> Eric Brombaugh wrote:
>>> I've designed a little I2S stereo audio codec board that will plug into
>>
>> Hopefully this isn't too picky but doesn't codec imply ADC and DAC?
>> It did initially confuse me.
>
> Never too picky for engineers! :)
>
> You're right - I was sloppy in describing the part as a codec. It's
> actually just an audio DAC. Sorry for any confusion.

I was also confused initially, but figured it out.

>>  > Not greedy at all - it's a nice goal to have. Unfortunately, a
>> combined
>>  > ADC/DAC codec requires at a minimum 5 I/O signals (mclk, sclk, lrclk,
>>  > di, do) and there are only 4 signals available on the Digilent 6-pin
>>  > connectors.
>>
>> Could a small CPLD be used make 5 signals fit on 4 pins? Maybe deriving
>> the lrclk from the sclk? I think there are CPLDs in the $1 range.

The LRCLK is really the strict divide down of SCLK but the phase is the
important information. The LRCLK is actually a synchronisation signal and
not a clock in its own right.

> Interesting idea. I'd probably start by muxing the SCLK and LRCLK onto
> one line using the MCLK and some synchronization bits. Any suggestions
> for a cheap CPLD that runs off of 3.3V and doesn't take up too much
> real-estate? I've done some stuff with Xilinx XC95 parts, but they're
> more like $5 - more expensive than the DAC I'm using now.

It can be done, but now it looks like creeping featurism is showing up.
Simple, cheap and now would be preferred IMHO. Doing an ADC board would not
be too hard either.

Cheers,
Magnus