[Fpga-synth] RAM Technique and the phLUTe

[Veronica Merryfield]

I had a thought - could you figure out a way to put in a short  
controlled decay at the note end, then clean the delay lines to zero  
then start fresh. You should be able to do this in a millisecond or two.

On 6-Apr-08, at 9:28 AM, Veronica Merryfield wrote:

>
> On 6-Apr-08, at 9:08 AM, Scott Gravenhorst wrote:
>
>> In my endeavor to tame those transients, I have an idea that may  
>> (or may not) work.
>>
>> The idea is to use two copies of the RAM structure used for the  
>> digital waveguides so that when a pitch change occurs, the system  
>> first makes a stretched or compressed copy (depending on pitch down  
>> or pitch up change respectively) in the "offline" RAM and then  
>> switches the system to "play" from the new RAM data.  I've devised  
>> an algorithm that should work, it needs an extension to the tuning  
>> tables to provide a reciprocal of the length value needed to  
>> compute the stretch or compress and to avoid division i
>> n the algorithm.  My rough calculations indicate that this copy  
>> process should take 2 sample times, or 20uS for 100KHz SR.
>>
>> I believe that a 20uS delay in pitch change is below the threshhold  
>> of human perception - ??
> Yes, it is. For a very sensitive person, a few ms is the lower  
> threshold.
>
>> My idea includes the use of dual port block RAM so that 2  
>> computations can occur simultaneously on the same RAM.
>>
>> The Xilinx doc on using block RAM says that the dual port RAM is  
>> symmetrical with two identical and independant ports.
>>
>> I'm taking this to mean that I can write to both ports  
>> simultaneously at different addresses.  ??
> You need to the read the spec on dual port carefully. Usually, it  
> mean a write and a read cycle can happen together but the actual  
> write and read happen on diffent clocks at the RAM. The  
> implementation usually takes advantage of higher speed access RAM OR  
> it provides two ports to ease system design but expects acceses on  
> different cycles. My use of it has been with pipelined CPU  
> architectures.
>>
>>
>> ----
>>
>> My first attempt will do this only with the Bore because I don't  
>> want to eliminate the transient completely, only tame it.  I'm  
>> hoping that leaving the Jet do what it wants to do will perhaps  
>> accomplish this.
>>
>> Since there are currently 14 free multipliers available, I could  
>> actually use 8 additional dedicated multipliers to create 2 more 35  
>> bit multipliers so I could do both the jet and the bore (the jet is  
>> 1/2 the length so it requires 1/2 the time or 1/2 the computational  
>> power).
>>
>> Does anyone have any thoughts at all about this idea? - it seems  
>> like it will be some work to make it happen and I'd like to bounce  
>> this off you people before I take the plunge.