[Fpga-synth] Another Question - State Machines

[Eric Brombaugh]

Scott Gravenhorst wrote:
> My state machine seems to be doing things that make no sense.  So I began looking at the coding examples in language templates and I see that for both Mealy and Moore, the examples go no larger than 16 states.  Could my problem be coming from the fact that I am trying to define a state machine with more than 16 states?

I doubt it - that would suggest a serious problem in the synthesis tool 
which although possible is unlikely. Consider an n-bit counter: that's a 
state machine with 2^n states. Although a degenerate case, it's 
certainly more than 16 in the limit.

OTOH, for mental clarity it's often useful to break large state machines 
down into hierarchies of smaller ones that are easier to think of and 
specify. These can be tested in isolation, then integrated into the 
whole context with greater confidence.

A few things to watch out for when coding state machines in Verilog -
* are your sensitivity lists in sync with the signals actually being used?
* do you have your blocking/non-blocking assignments correct?
* do your default & unused states have paths back to the normal flow?
* are all asynchronous inputs synchronized to the local clock before 
hitting the state machine logic?

Eric