[Fpga-synth] ISE Inferrence and Instantiation Question

[Eric Brombaugh]

Scott Gravenhorst wrote:
> When ISE infers something like block RAM, is there a way to see how the primitive was instantiated?  

Use the 'netgen' command to convert the .ngc file that comes out of XST 
into a verilog file:

netgen -ofmt verilog -w infile.ngc outfile.v

Warning: this file is generally used only for gate-level simulations and 
isn't intended to be particularly readable. The hierarchy is flattened 
and a lot of the netnames will have been munged. Tracking down the 
instance you want can be entertaining.

> I.e., so that the instantiation could be used in place of the code that inferred it?

Any particular reason you prefer to instantiate rather than infer?

Eric