[Fpga-synth] Learning FPGA Design

[Dave Manley]

(Eric has already posted a followup, that covers some of what I talk 
about below, but I'll post this anyway)

As a followup, I was just looking at the HDL Coding Techniques examples 
in the XST users guide and noticed the following:

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module v_fsm_3 (clk, reset, x1, outp);
input clk, reset, x1;
output outp;

reg outp;
reg [1:0] state;
reg [1:0] next_state;

parameter s1 = 2'b00; parameter s2 = 2'b01;
parameter s3 = 2'b10; parameter s4 = 2'b11;

initial begin
   state = 2'b00;
end
^^^^^^^^^^^^^^^^!

always @(posedge clk or posedge reset)
begin
   if (reset) state <= s1;
   else state <= next_state;
end

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They have a reset clause, but they also have an initial block!!!???

An 'initial' block isn't considered synthesizable.  If 'state' needs to 
be initialized then the reset signal does this.  There's no need for an 
initial block.  (I guess the exception to this is in an FPGA where there 
is a means to set the initial state of everything, and you could imagine 
relying on an initial block.  This assumes you want to reconfigure the 
FPGA everytime you want to reset the logic you've put in the FPGA. 
Normally this isn't the case, you don't want the penalty of a 
reconfiguration when all you need is a reset.)

Does XST handle this type of coding?  It is unfortunate they give broken 
examples in their user guide.  I guess it is to much to ask that they'd 
verify each and every example. ;-)

-Dave