[Fpga-synth] Learning FPGA Design

[Eric Brombaugh]

Dave Manley wrote:

> Syntactically, the only thing that is odd is the 'reg QQ 
> = 0'.

Before using FPGAs I would have agreed with you 100% on this issue, and 
I still don't do declaration/initialization in my day-to-day code. The 
main reason is that I come from an ASIC background where this just plain 
doesn't make sense.

That said though, due to the built-in initialization that the FPGA 
configuration process gives you, this is actually a more accurate model 
for the way an FPGA design really works.

Assuming X on startup and giving an explicit reset is still the most 
bullet-proof way to design though. The more pessimistic modeling 
provided by 'all X' will help you find some start-up and deadlock states 
that aren't found by assuming 'all 0' states.

> I am unfamiliar with XST, but have heard things over the years, and have 
> been impressed with what you've been able to accomplish using it.  I 
> believe Synopsys Design Compiler and Synplicity Synplify would have both 
> compiled all of your examples correctly.

I've used Synopsys DC, ancient Xilinx stuff and now lately XST. XST 
isn't at all bad, but it does have a few problems. I've personally 
submitted 3 testcases for issues that I've seen across ISE 8.2 - 9.2.

Not bad for a free tool though. I tend to code at a fairly high level 
(very little explicit instantiation) and it manages to infer my intent 
almost all the time - even with things like V4 DSP48s with all the 
trimmings.

> I recommend adopting a very minimalist Verilog coding standard where you 
> use only what you know to work perfectly.  If you had access to a lot of 
>   professionally written verilog, you'd see for the most part people 
> keep it very simple and only go down tried and true paths.

Seconded.

Eric