[Fpga-synth] Learning FPGA Design

[Dave Manley]

Hi Scott,

I have to agree Eric's comments.  I don't see anything wrong with any of 
your examples.  Syntactically, the only thing that is odd is the 'reg QQ 
= 0'.  Typically, I'd do something like this:

reg QQ;
always @ (posedge clk)
   if (reset)
     QQ <= 0;
   else
     QQ <= ~QQ;

I have never seen initializations done in the declaration in Verilog 
(maybe in a test bench, but not in synthesizable code).  It is a common 
'C' coding practice, but I don't usually do it in C either, and instead 
explicitly initialize variables.

Since this flop is just toggling, if you don't care about its 
relationship to anything else, both the initialization and reset clause 
is really unneeded.  I wonder if your reg declaration and initialization 
to 0 is doing anything unintended.

I am unfamiliar with XST, but have heard things over the years, and have 
been impressed with what you've been able to accomplish using it.  I 
believe Synopsys Design Compiler and Synplicity Synplify would have both 
compiled all of your examples correctly.

I recommend adopting a very minimalist Verilog coding standard where you 
use only what you know to work perfectly.  If you had access to a lot of 
  professionally written verilog, you'd see for the most part people 
keep it very simple and only go down tried and true paths.

HTH,
Dave