[Fpga-synth] Block RAM Inferrence

[Dave Manley]

Hi Scott,

Have you looked at the XST User Guide?

For small rams (<256 or <512 total bits depending on the device) XST 
will automatically use distributed ram.  See Table 2-63 in the 9.2i XST 
User Guide.

Also take a look at the "RAM_STYLE" constraint.  It allows the user to 
override the automatically chosen inferred ram.

I haven't used these because I have access to Synplicity and there is a 
comment you can embed in your source to direct the ram inference.  I've 
found for large rams running at high speeds it is better to use Coregen. 
    My goal was a 128 x 8192 ram running at 250MHz.  Using inferred rams 
this was nearly impossible, but using coregen it is easy to get 300MHz 
clock speeds.  Watch out for things that get thrown in for "free".  By 
default synplicity throws in logic for simulataneous read and write.  I 
don't know if XST has similar quirks.

Also in the XST guide there are examples coding examples for various 
ram/rom styles.  Looking section 2, "RAMs and ROMs Coding Examples".

HTH,

Dave

Scott Gravenhorst wrote:
> Just to see what would happen, I tried to infer block RAM using something
> like this:
> 
> reg [17:0] BRAM [0:16383];
> 
> The FPGA has enough RAM to do this and the structure of it can accomodate
> this, but after a VERY long XST time, the report showed that ISE was
> attempting to use distributed RAM to do this (showing over 200% usage so I
> knew this wouldn't work).  I had removed all hand instantiated block RAMs
> first, except for the PicoBlaze ROM.  There is also one multiplier used in
> the design, so there are 18 block RAMs that are available - just enough to
> do the above declaration.
> 
> A warning finally appeared saying that the data was clocked asynchronously
> and that if it could be made synchronous, ISE could infer block RAM.  It
> then said that I should consult my documentation for proper source code
> construction to accomplish this.  After two hours of cranking and grinding,
> I canceled the task.
> 
> Could anyone please tell me what document this is?  Or how I should
> construct my code to make the block RAM inferrence happen?
> 
> I'm trying to use as much inferrence as possible because the code is
> cleaner and more portable to other FPGA platforms.
> 
> -- ScottG
> 
> -------------------------------------------------------------
> 
> -- Scott Gravenhorst
> -- GateMan II - Xilinx Spartan-3E Based MIDI Synthesizer with SVF
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> -- When the going gets tough, the tough use the command line.
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