[Fpga-synth] Block RAM Inferrence

[Scott Gravenhorst]

Just to see what would happen, I tried to infer block RAM using something
like this:

reg [17:0] BRAM [0:16383];

The FPGA has enough RAM to do this and the structure of it can accomodate
this, but after a VERY long XST time, the report showed that ISE was
attempting to use distributed RAM to do this (showing over 200% usage so I
knew this wouldn't work).  I had removed all hand instantiated block RAMs
first, except for the PicoBlaze ROM.  There is also one multiplier used in
the design, so there are 18 block RAMs that are available - just enough to
do the above declaration.

A warning finally appeared saying that the data was clocked asynchronously
and that if it could be made synchronous, ISE could infer block RAM.  It
then said that I should consult my documentation for proper source code
construction to accomplish this.  After two hours of cranking and grinding,
I canceled the task.

Could anyone please tell me what document this is?  Or how I should
construct my code to make the block RAM inferrence happen?

I'm trying to use as much inferrence as possible because the code is
cleaner and more portable to other FPGA platforms.

-- ScottG

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-- Scott Gravenhorst
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