[Fpga-synth] Correction

[Scott Gravenhorst]

Dear All,

I had made a statement awhile back that I need to amend/correct.  It was
regarding inferring RAM instead of flipflops in a Verilog design.  I was
having problems converting the GateMan-I design to use RAM instead of
flipflops and couldn't get ISE to infer RAM.  I then set about hand
instantiating RAMs.  At the time, I blamed PicoBlaze for confusing ISE and
causing it to infer flipflops instead of RAM when a declaration like this
is used:

reg [17:0] myObject [0:3];

At that time, I had done an experiment that seemed to prove this to be
correct.  Unfortunately, my server suffered a doofus thing and I erased the
source code for that test project.  Sadly, I cannot now revisit the
project.  Yesterday, I created a new, similar test and the results were
that RAM is inferred just fine with PicoBlaze instantiated and connected.

So my statement was incorrect, PicoBlaze was not the problem.  It was my
misunderstanding of the inferrence process that caused my problem.  I know
this now because I've been working on the PolyDaWG project to use RAMs
instead of hundreds of flipflops.

The problem was (how could this be?) my design.  I've discovered that 1)
the mere declaration like the one above is only a small part of inferring
RAM.  2) if there are combinatorial assigns which use myObject such as:

assign something = myObject[2];

the design will infer flip flops because the above use isn't really an
addressable memory object, it is, in fact, a row of flipflops.

Also 3) if the design contains too many places where data is clocked into
myObject, flipflops will be inferred.  

I found that rearranging the state machine logic so that data is moved into
the object in only one state, the design will then contain RAM instead of
flip flops.

I worked on each register object one at a time and ascertained the inferred
RAM vs flipflop instantiation by looking at the RTL schematic.  The
inferred RAMs are named Mram_objectname1, so it was easy to find them.  Now
all of the targetted objects are inferred as RAM and flipflop count has
been drastically reduced.  Now I just have to "fix" the project since
something I did has broken it.  In some cases, the calculations required
for stuffing the memory object were complex and I needed to place an
intermediary register between the calculation and the clocking of the
result into the memory object.  Done this way, RAM is inferred, the beauty
of this is that I don't have to write a bunch of cheesey logic to clock
hand instantiated RAMs, ISE does this nicely and efficiently.

I apologize to all for my misleading statement.  Go ye therefore and use
PicoBlaze.

-- ScottG

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-- Scott Gravenhorst
-- GateMan II - Xilinx Spartan-3E Based MIDI Synthesizer with SVF
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