[Fpga-synth] Jitter

[Magnus Danielson]

From: Scott Gravenhorst <music.maker at gte.net>
Subject: [Fpga-synth] Jitter
Date: Sun, 18 Nov 2007 17:10:53 -0700
Message-ID: <200711190110.lAJ1AqoU031100 at linux7.lan>

> For a Spartan-3E, it looks like the jitter tolerance of the DLL system is
> +/- 300 pico seconds for clock input frequencies less than or equal to 150
> MHz.  The S3Esk board user doc doesn't have jitter specs per se for the 50
> MHz on board clock.  They only state:
> 
> The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle.
> The oscillator is accurate to ±2500 Hz or ±50 ppm.
> 
> I think that's a 2 pico second span.  I know that's not the same as jitter.

Yeah, that is a common misstake. Good thing you pointed out that it is not the
same.

If you have a 2 ps(RMS) clock you are most of the times home free. There are
better clocks when in need.

>  I would hope that the hardware clock chosen would complement the jitter
> tolerance of the DLL.

I would think so too. Best thing is to pull the datasheet. It is the cycle-to-
cycle jitter which will be given, probably in the bogusity peak-to-peak form.

> Also, the PicoBlaze docs I looked at are sort of old.  They state a max
> rate of 43 MIPS for a Spartan-3 not a Spartan-3E.  The doc says to look at
> the ISE trace report.  My design is showing 109.9 MHz with the longest
> delay being associated with kcpsm3.  That would indicate that I should be
> able to run it at 100 MHz assuming my jitter isn't excessive.  

I agree with your conclusion here.

Cheers,
Magnus