[Fpga-synth] Jitter

[Dave Manley]

Scott Gravenhorst wrote:
> For a Spartan-3E, it looks like the jitter tolerance of the DLL system is
> +/- 300 pico seconds for clock input frequencies less than or equal to 150
> MHz.  The S3Esk board user doc doesn't have jitter specs per se for the 50
> MHz on board clock.  They only state:
>
> The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle.
> The oscillator is accurate to ±2500 Hz or ±50 ppm.
>
> I think that's a 2 pico second span.  I know that's not the same as jitter.
>  I would hope that the hardware clock chosen would complement the jitter
> tolerance of the DLL.
The +/-50ppm is just an accuracy number - it considers initial set 
frequency, aging, temperature and voltage variation. These sources of 
inaccuracy lead to drift over time, but not jitter.  For most purposes 
any reasonably designed crystal oscillator, on a reasonably designed 
board (good power and signal integrity) can be assumed jitter free (did 
I put enough weasel words in there?).  To see the DCM jitter use a dual 
trace storage scope, trigger on the oscillator's output and watch the 
DCM output.  Make sure you've got a solid trigger.

-Dave