[Fpga-synth] Jitter

[Scott Gravenhorst]

For a Spartan-3E, it looks like the jitter tolerance of the DLL system is
+/- 300 pico seconds for clock input frequencies less than or equal to 150
MHz.  The S3Esk board user doc doesn't have jitter specs per se for the 50
MHz on board clock.  They only state:

The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle.
The oscillator is accurate to ±2500 Hz or ±50 ppm.

I think that's a 2 pico second span.  I know that's not the same as jitter.
 I would hope that the hardware clock chosen would complement the jitter
tolerance of the DLL.

Also, the PicoBlaze docs I looked at are sort of old.  They state a max
rate of 43 MIPS for a Spartan-3 not a Spartan-3E.  The doc says to look at
the ISE trace report.  My design is showing 109.9 MHz with the longest
delay being associated with kcpsm3.  That would indicate that I should be
able to run it at 100 MHz assuming my jitter isn't excessive.  

-- ScottG

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-- Scott Gravenhorst
-- GateMan II - Xilinx Spartan-3E Based MIDI Synthesizer with SVF
-- PolyDaWG/8 - 8 Voice FPGA Polyphonic MIDI Synthesizer
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