[Fpga-synth] Interesting

[Magnus Danielson]

From: Eric Brombaugh <ebrombaugh at earthlink.net>
Subject: Re: [Fpga-synth] Interesting
Date: Sun, 18 Nov 2007 18:58:17 -0700
Message-ID: <E7A48D7B-9B15-4990-920F-D83EC9C1BBD3 at earthlink.net>

> Heed the words of the master!
> 
> Thanks for the advice - I don't usually spend much time worrying about  
> jitter, but this is helpful. I'll take the suggestions of a guy with  
> atomic clocks as gospel.

Heh, thanks for the vote of confidence! It should however be pointed out that
while the atomic clocks and GPS receivers gives me good frequency precision,
it should not be confused with the jitter statistics which requires high
resolution counters and statistical analysis for propper handling.

You can get a fairly good distance with modern scopes, some of them now include
fancy jitter analysis options, but already getting trigger histogram can be
more than enought for starters.

> I've used DCMs several times and one thing I might suggest: If the  
> reference clock is ever stopped they tend to go out into the weeds.  
> It's helpful to have the reset input brought out to a controllable  
> point to correct this.

Oh, you *DO* want to check the DCM lock status!

While I may scare some people off by my reading of acient rituals and scary
look while swinging the chicken, don't confuse this as me discuraging the use
of DCMs. Rather the opposite, if handled with due care, they can help you solve
hairy things. Just don't overestimate their abilities!

The core idea for the DCMs is that they is a long chain of inverters creating a
delay. The DCM switches tap on that delay-chain to match delay for the
feedback. Switching in interesting patterns gives frequency multiplication.
Kind if neat, very digital and efficient to implement in CMOS. Not the best
strategy for low jitter. A delay step can be in the rane of about 20 ps.
This may or may not be a problem. If you upset it, it steps many delay steps.

Cheers,
Magnus