[Fpga-synth] Interesting

Magnus Danielson magnus at rubidium.dyndns.org
Sun Nov 18 23:22:59 CET 2007


From: Scott Gravenhorst <music.maker at gte.net>
Subject: [Fpga-synth] Interesting
Date: Sun, 18 Nov 2007 14:00:09 -0700
Message-ID: <200711182200.lAIM09pk020038 at linux7.lan>

> Well, I was messing around with trying to reduce the delays in my design to
> increase the maximum operating frequency, I just kicked it over 100 MHz!  I
> have a bad habit of daisy chaining mux logic.  Pipelining fixes this.  Now
> I shall have to think very seriously about using SDRAM since at 100 MHz,
> the design would be alot faster (to get to 100 MHz, I only added 8 state
> times to the state machine logic, so while there are a few more states to
> do, they can be done twice as fast.
> 
> However, I'll bet using a DCM is probably the usual major PITA.

DCMs are nice, but you need to have a low jitter clock to start with or else
you will have problem, especially if you use the clock multiplication feature.
The DCM will not clean up jitter on the input, it isn't a PLL, but there are
similarities in that there is a feedback loop.
If you have too high jitter, the DCM may over-react and that results in bigger
jitter.
If you do frequency multiplication, the period becomes shorter for the same
amount of jitter (think about time here).

Too high jitter will cut down the allowed delay. So even if the synthesis tools
give you thumb up, higher jitter than expected will cause bit errors and those
can creep in and cause very strange results. This is especially important for
high speed DDR memory interfaces. Some DDR and QDR chips does not handle clock
jitter well and blows it up alot. Reducing jitter at the clock source is what
makes things manageable.

Synchronous design only give you a convenient simplification for design, just
as digital levels do. You need to work on the fine-grained details to be
allowed to work in that simplified world. The electroncs is analogue after all.

I welcome the addition of propper PLLs in newer FPGAs. Solves some of the
design problems. Complements DCM well if used wisely.

Cheers,
Magnus


More information about the Fpga-synth mailing list