[Fpga-synth] Terminology Question

[Magnus Danielson]

From: Scott Gravenhorst <music.maker at gte.net>
Subject: [Fpga-synth] Terminology Question
Date: Thu, 07 Jun 2007 06:54:46 -0700
Message-ID: <200706071354.l57DsjaB003359 at linux7.lan>

> This has been bugging me for a long time - "pipeline".  I now believe that
> I understand the term, but for the life of me, "pipeline" gave me the wrong
> impression when I first started seeing it in documentation and discussion.
>  To me, the process of using registers to clock results of logical or
> arithmetic calculations is more like the locks of a canal than a pipeline.
>  That is, a pipe (as in for fluids) has no "gates" and the contents is
> allowed to simply flow, utterly unimpeded.  This actually reminds me more
> of a simple chain of logic such as multiplier feeding adder feeding
> multiplier feeding whatever without pipeline registers.

For a real pipeline you have regular stations, pump stations. This to overcome
the friction.

> I understand that pipelining is the technique of arranging logic in such a
> way that the result of a calculation is placed on the inputs of a register
> and clocked with a system clock where the clock period is long enough that
> the calculation result is valid and settled before the edge of the clock. 

Indeed.

>   The output of the register is presented to more calculation logic and
> registered if necessary.  The process is repeated until the final output of
> the calculation is available at the last register stage.  The system must
> "know" at which clock the final result is available (such as with a simple
> state machine).

Indeed.

> A couple of questions:
> 
> 1) Why is this called "pipelining"?  I'm interested in a historical
> perspective if there is one.

I have never thought about this. But I guess someone coined it, probably back
in the 60thies or so. Maybe even Seymor himself. It was a core concern when
the MIPS and RISC projects where running at Standford and Berkley. I beleive
the tecnique was already well estabilshed by then anyway. The Cray-1 was for
instance certainly pipelined, but I belive this is true also for its
predecessors CDC 6600, 7600 and 8600 (from the top of my head). CDC 6600 used
score-boarding where as IBM came up with out of order execution (aka Tomasulo
algoritm). While these are as such not pipelining, they are techniques which
only makes sense in pipelined processors and thus indicate the existence of
the pipelining technique.

> 2) I see WebPACK telling me that the "performance of muliplier XYZ can be
> improved by using pipelining".  However, I don't understand what is meant
> by "improved performance" when if the multipliers are strung together, the
> result can actually be available sooner than if the multipliers are all
> cascaded through pipelining.

You can increase the through-put as you can raise the clock frequency. 

> 3) Are there obvious "never do" or "always do" rules that I am missing
> regarding this?  I.e., I can design a calculation that takes (eg) 45
> nanoseconds.  Why wouldn't I simply use a 50 nanosecond clock?  Do I only
> need to use pipelining when my design demands a faster clock for other reasons?

There are a bunch of "do" and "dont's". Many of them is obvious once you have
familiarized yourself with the technique.

> This was getting me into trouble before I understood timing constraints...

I can imagine.

> I know this isn't specifically about synths, so if there's a better place
> to post this, please let me know.

This is a perfectly good place to ask. We here need to understand it never the
less.

Cheers,
Magnus