[Fpga-synth] Terminology Question

[Mike Ravkine]

Scott Gravenhorst wrote:
> A couple of questions:
>   
I will try to answer them..
> 1) Why is this called "pipelining"?  I'm interested in a historical
> perspective if there is one.
>   
I'm not sure, but perhaps it's a reference to the assembly line method 
of producing cars.  Pipelining was originally invented for CPUs.  A CPU 
needs to go through several stages (fetch, decode, execute, write-back 
at the very minimum).  So each instruction takes 4 cycles to execute.  A 
pipelined CPU would fetch, decode, execute and write-back on every 
cycle.. so there are 4 instructions really being executed at any point 
in time, giving an average of 1 cycle/instruction, despite the fact that 
it's still taking 4 cycles to execute them.

In Synths, we face a similar problem.  Computing the output sample often 
requires the computation of many intermediate values.  So instead of 
generating these values step-by-step, we allow the computation of 
multiple output samples concurrently (similarly to how a pipelined cpu 
allows the execution of multiple instructions concurrently).
> 2) I see WebPACK telling me that the "performance of muliplier XYZ can be
> improved by using pipelining".  However, I don't understand what is meant
> by "improved performance" when if the multipliers are strung together, the
> result can actually be available sooner than if the multipliers are all
> cascaded through pipelining.
>   
It's referring to the maximum attainable clock rate.  A pipelined 
multiplier can simply be clocked faster (but will have an output latency 
of one or more cycles).
> 3) Are there obvious "never do" or "always do" rules that I am missing
> regarding this?  I.e., I can design a calculation that takes (eg) 45
> nanoseconds.  Why wouldn't I simply use a 50 nanosecond clock?  Do I only
> need to use pipelining when my design demands a faster clock for other reasons?
>   
The calculation may take 45ns yes, but there are also routing delays and 
wire delays to consider, as well as setup and hold times on the flip 
flops.  This can make the 'real' delay (after P&R) much higher then you 
expect.  The larger your system gets, the worse these transport delays 
become.   Sometimes pipeline flops are inserted with no logic between 
them.  These have nothing to do with splitting up the computation 
itself, but simply to get the inputs of the next computation stage to be 
physically closer to the next bit of computation logic, and so reducing 
those pesky routing and transport delays.

You are essentially right though, if you are happy with the clock rate 
you are getting without pipelining then there is no need to introduce 
it.and the added complexity it brings.
> This was getting me into trouble before I understood timing constraints...
>
> I know this isn't specifically about synths, so if there's a better place
> to post this, please let me know.
>   
I completed a course on pipelining a few months ago, so most of it is 
still fresh in my mind .. if you have any more questions, feel free to 
mail me off list.

--Mike