[Fpga-synth] Terminology Question

[Scott Gravenhorst]

This has been bugging me for a long time - "pipeline".  I now believe that
I understand the term, but for the life of me, "pipeline" gave me the wrong
impression when I first started seeing it in documentation and discussion.
 To me, the process of using registers to clock results of logical or
arithmetic calculations is more like the locks of a canal than a pipeline.
 That is, a pipe (as in for fluids) has no "gates" and the contents is
allowed to simply flow, utterly unimpeded.  This actually reminds me more
of a simple chain of logic such as multiplier feeding adder feeding
multiplier feeding whatever without pipeline registers.

I understand that pipelining is the technique of arranging logic in such a
way that the result of a calculation is placed on the inputs of a register
and clocked with a system clock where the clock period is long enough that
the calculation result is valid and settled before the edge of the clock. 
  The output of the register is presented to more calculation logic and
registered if necessary.  The process is repeated until the final output of
the calculation is available at the last register stage.  The system must
"know" at which clock the final result is available (such as with a simple
state machine).

A couple of questions:

1) Why is this called "pipelining"?  I'm interested in a historical
perspective if there is one.

2) I see WebPACK telling me that the "performance of muliplier XYZ can be
improved by using pipelining".  However, I don't understand what is meant
by "improved performance" when if the multipliers are strung together, the
result can actually be available sooner than if the multipliers are all
cascaded through pipelining.

3) Are there obvious "never do" or "always do" rules that I am missing
regarding this?  I.e., I can design a calculation that takes (eg) 45
nanoseconds.  Why wouldn't I simply use a 50 nanosecond clock?  Do I only
need to use pipelining when my design demands a faster clock for other reasons?

This was getting me into trouble before I understood timing constraints...

I know this isn't specifically about synths, so if there's a better place
to post this, please let me know.


-- ScottG

-------------------------------------------------------------

-- Scott Gravenhorst
-- GateMan I - Xilinx Spartan-3E Based MIDI Synthesizer
-- FatMan: home1.gte.net/res0658s/fatman/
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-- When the going gets tough, the tough use the command line.