[Fpga-synth] Using Xilinx primitives in GHDL?

[Rainer Buchty]

Hello everyone,

did any of you succeed in using the Xilinx primitives from within GHDL? 
I know there's a recent discussion on comp.arch.fpga where this was 
discussed to some extent, but when I try following that very same order 
of compilation I'm just stuck with the following:

buchty at archimobil:~/proj/vhdl/unisim$ ghdl -a --ieee=synopsys -fexplicit 
unisim_VCOMP.vhd

buchty at archimobil:~/proj/vhdl/unisim$ ghdl -a --ieee=synopsys -fexplicit 
unisim_VPKG.vhd

buchty at archimobil:~/proj/vhdl/unisim$ ghdl -a --ieee=synopsys -fexplicit 
unisim_VITAL.vhd
unisim_VITAL.vhd:1180:12: primary unit "vcomponents" not found in 
library "unisim"
/usr/lib/ghdl/bin/ghdl: compilation error

Any idea?

Happy new year,
 	Rainer