[Fpga-synth] RAM infer question

[Eric Brombaugh]

On Dec 29, 2007, at 1:01 PM, Scott Gravenhorst wrote:

> I'm trying to infer Xilinx distributed RAM by using the coding  
> examples in
> the language templates.  For distributed RAM, they show a block with a
> single point where clocked writing to the selected location occurs  
> and an
> asynchronous read.
>
> When I do this with my code, I don't get flipflops, I get INFO  
> remarks that
> the RAM will be implemented on LUTs because of the asynchronous reads.
>
> I assume this remark is not a bad thing (not a warning, just an  
> info) and I
> can ignore it because I'm doing it on purpose? (these are small RAMs  
> and I
> don't want to target block RAM)

In Xilinx it's actually more desirable to infer LUTs for distributed  
RAM because you can store 16 bits in a LUT, but only 1 bit in a FF. So  
I'd say you're doing it right.

>
> FPGA synth content: My project is a 32 NCO additive MIDI monosynth.

Sounds cool. Question: you're using separate NCOs for all the  
harmonics? The only reason to do that is if you want anharmonics - if  
you want exact 1x, 2x, 3x, ... etc then you can use just 1 NCO and  
shift/add networks for the higher harmonic phases.

Eric