[Fpga-synth] RAM infer question

[Scott Gravenhorst]

I'm trying to infer Xilinx distributed RAM by using the coding examples in
the language templates.  For distributed RAM, they show a block with a
single point where clocked writing to the selected location occurs and an
asynchronous read.

When I do this with my code, I don't get flipflops, I get INFO remarks that
the RAM will be implemented on LUTs because of the asynchronous reads.

I assume this remark is not a bad thing (not a warning, just an info) and I
can ignore it because I'm doing it on purpose? (these are small RAMs and I
don't want to target block RAM)

FPGA synth content: My project is a 32 NCO additive MIDI monosynth.

-- ScottG

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-- Scott Gravenhorst
-- GateMan-III - FPGA Based Monophonic MIDI Synthesizer with SVF
-- PolyDaWG/8 - FPGA Based 8 Voice Polyphonic MIDI Synthesizer
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-- When the going gets tough, the tough use the command line.