[Fpga-synth] I Think I Know Why It's Happening

[Scott Gravenhorst]

I wrote code to sum the pickup output data with the RAM address and send
that to the DAC.  

What I saw was a constant pitch sawtooth and a pickup waveform that was
*not* synched to the saw.  Played around a bit more, I noticed that as the
bandwidth of the IIR filter is increased, the difference between the pickup
output and the saw frequency becomes less and less.  If I max the
bandwidth, the waveforms are synched.

What I believe is happening is that the delay of the filter, when bandwidth
is low, is contributing an extra delay state to the delay line.  The actual
length is then one more and that causes the unsynched signals.  It also
makes sense because low bandwidth means more filter delay.

Now to try to figure out how to fix it, but it seems a conundrum at the
moment.  Is there a common method to fix something like this?

-- ScottG

-------------------------------------------------------------

-- Scott Gravenhorst
-- GateMan I - Xilinx Spartan-3E Based MIDI Synthesizer
-- FatMan: home1.gte.net/res0658s/fatman/
-- NonFatMan: home1.gte.net/res0658s/electronics/
-- When the going gets tough, the tough use the command line.