[Fpga-synth] Delay Line Theory

[Eric Brombaugh]

Scott Gravenhorst wrote:

>> Wait a second - is ptr + PU the input and the ptr address the only read 
>> output of the delay line? 
> 
> No, ptr + PU is used only as the address of the source of DAC data.  Reading and writing
> the RAM is done with ptr unmodified.  Only an increment is ever applied to ptr.  ptr + PU
> is never saved back into ptr.

Ok - I must have misunderstood. Referring back to the diagram on the 
Wiki, your delay line actually has two outputs - one of which has fixed 
delay and feeds back to the waveguide and another of which has variable 
delay and goes only to the output DAC.

In that case, varying the tap delay will produce a phase shift and 
doppler will occur while it's moving.

That said though, your bug sounds like you're feeding the variable delay 
output into the waveguide instead of the fixed delay.

> I want to spend more time looking at your code.  Mine is more hamfisted I think.

Bear in mind that the code I sent has only one output with variable 
delay and no fixed delay. That functionality wouldn't be hard to add 
though...

Eric